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L6238S
12V SENSORLESS SPINDLE MOTOR CONTROLLER
PRODUCT PREVIEW
12V OPERATION 3A, THREE-PHASE DMOS OUTPUT (TOTAL Rdson 0.52) NO HALL SENSORS REQUIRED DIGITAL BEMF PROCESSING LINEAR OR PWM CONTROL STAND ALONE OR EXT. DRIVER SHOOT-THROUGH PROTECTION THERMAL SHUTDOWN DESCRIPTION The L6238S is a Three-Phase, D.C. Brushless Spindle Motor Driver system. This device features both the Power and Sequence Sections. Higher Power Applications can be activied with the addition of an external Linear Driver, or by operating the Internal Drivers in PWM. Motor Start-Up, without the use of Hall Sensors, can be achieved either by an internal start-up algorithm or by manually sequencing the Output Drivers, using a variety of User-Defined Start-UP Algorithms. BLOCK DIAGRAM
VL FALIGN OUTPUT ENABLE RUN/ BRAKE PWM/ SLEW PWM LIN PWM COMP PWM TIM CHARGE PUMP VANALOG BIAS ONE-SHOT SLEW-CTRL POWER STAGE SYS CLOCK SYSTEM CLOCK ALIGN + GO START-UP
PLCC44
PQFP44
TQFP64
ORDERING NUMBERS: L6238S (PLCC44) L6238SQA (PQFP44) L6238SQT (TQFP64)
Protection features include Stuck Rotor\Backward Rotation Detection and Automatic Thermal Shutdown.
CPUMP1 CPUMP2 CPUMP3
VPOWER
SEQ INCR MONO/SEQ CTRL
BRAKE DELAY SEQUENCER
TDLY(0) TDLY(1) TDLY(2) MASK DLY DIGITAL DELAY MONO DET
ZERO CROSSING DETECTOR
+
BEMF + SENSE +
OUT A OUT B OUT C CTR TAP
-
SPIN SENSE
TOGGLE
DIVIDE BY N
RSENSE1 + DRV CNTL RSENSE2
OT-WARN
THERMAL SHUTDOWM
AV=4V/V CSA
GND CSA INPUT
SEL POL
FMTR
VCTRL
GM COMP GATE DRIVE
D95IN232
October 1995
1/31
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6238S
ABSOLUTE MAXIMUM RATINGS
Symbol BVdss VPower VLogic VAnalog Vin C storage Imdc Impk Ptot Output Brakdown Voltage Motor Supply Voltage Logic Supply Voltage Analog Supply Voltage Input Voltage Charge Pump Storage Capacitor Motor Current (DC) (TQFP64 only) (PLCC44 and PQFP44) Peak Motor Current (Pulsed: Ton = 5ms, d.c. = 10%) Power Dissipation at Tamb = 50 C (PLCC44) (TQFP64) (PQFP44) Storage and Junction Temperature Parameter Value 17 15 7 15 -0.3 to 7 4.7 3 2.5 5 2.3 1.7 1.3 -40 to 150 Unit V V V V V F A A A W W W C
Ts
THERMAL DATA
Symbol R th (j-amb) Parameter Thermal Resistance Junction-Ambient PLCC44 34 PQFP44 45 TQFP64 45 Unit C/W
Those Thermal Data are valid if the package is mounted on Mlayer board in stillair
PIN CONNECTION PLCC44 (Top view)
CHARGE PUMP 2
BRAKE DELAY
MASK DELAY
CENTER TAP
SPIN SENSE
PWM/SLEW
OUTPUT B
RSENSE 1
VPOWER
GND
6 GND CHARGE PUMP 1 CHARGE PUMP 3 OUTPUT A VPOWER VANALOG N.C. TDLY(0) TDLY(1) TDLY(2) GND 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND GATE DRIVE GM COMP OUTPUT C RSENSE 2 CSA INPUT VCONTROL N.C. FMOTOR VLOGIC GND
18 19 20 21 22 23 24 25 26 27 28 OUTPUT ENABLE RUN/BRAKE SEQ. INCREMENT PWM LIMIT TMR SELECT POLE PWM/LINEAR MONO/SEQINC CTRL SYSTEM CLOCK PWM COMP OTWARN FALIGN
D95IN245
2/31
GND
L6238S
PIN CONNECTION PQFP44 (10x10) (Top view)
CHARGE PUMP 3 CHARGE PUMP 1 2
OUTPUT A
VANALOG
VPOWER
TDLY(2)
TDLY(1)
TDLY(0)
GND
11 10 OTWARN SELECT POLE PWM LIMIT TIMER PWM/LINEAR OUTPUT ENABLE RUN/BRAKE SEQ. INCREMENT SYSTEM CLOCK MONO/SEQINC CTRL FALING PWM COMP. 12 13 14 15 16 17 18 19 20 21 22
9
8
7
6
5
4
3
GND 1 44 43 42 41 40 39 38 37 36 35 34 GND CHARGE PUMP 2 RSENSE 1 BRAKE DELAY SPIN SENSE OUTPUT B PWM/SLEW CENTER TAP VPOWER MASK/DELAY GND GND
23 24 25 26 27 28 29 30 31 32 33 VCONTROL RSENSE 2 GATE DRIVE CSA INPUT OUTPUT C GM COMP FMOTOR GND VLOGIC N.C.
D95IN243
PIN CONNECTION TQFP64 (Top view)
CHARGE PUMP 3 CHARGE PUMP 1
N.C.
OUTPUT A
OUTPUT A
VANALOG
VPOWER
VPOWER
TDLY(2)
TDLY(1)
TDLY(0)
GND
GND
GND
GND 2
16 15 14 13 12 11 10 GND N.C. N.C. OTWARN SELECT POLE PWM LIMIT TMR PWM/LINEAR OUTPUT ENABLE RUN/BRAKE SEQ. INCREMENT SYSTEM CLOCK MONO/SEQINC CTRL FALIGN PWM COMP N.C. GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9
8
7
6
5
4
3
GND 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND GND CHARGE PUMP 2 RSENSE 1 RSENSE 1 BRAKE DELAY SPIN SENSE OUTPUT B OUTPUT B PWM/SLEW CENTER TAP VPOWER VPOWER MASK DELAY GND GND GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VLOGIC CSA INPUT RSENSE 2 RSENSE 2 GM COMP GND GND GND GATE DRIVE VCONTROL FMOTOR OUTPUT C OUTPUT C GND N.C.
N.C.
D95IN244
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L6238S
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64 1 2 3 4 5 6, 7, 17, 29, 39, 40 8 9 10 11, 42 12 13, 32 39 40 41 42 43 1, 11, 23, 33, 34, 44 2 3 4 5, 36 6 7, 26 56, 57 58 59 60, 61 62 * Name OUTPUT B SPIN SENSE BRAKE DELAY R sense 1 CHARGE PUMP 2 GROUND I/O I/O O I O I S Function DMOS Half Bridge Output and Input B for Bemf sensing. Toggless at each Zero Crossing of the Bemf. Energy Recovery time constant, defined by external R-C to ground. Outputs A+B connections for the Motor Current Sense Resistor to ground Negative Terminal of Pump Capacitor. Ground terminals.
4 5 6, 7 9, 10, 52, 53 11 8, 18, 19, 31, 41 12 13 14 20 21 22 23 24 25 26 27 28 29
CHARGE PUMP 1 CHARGE PUMP 3 OUTPUT A Vpower Vanalog N.C
I O I/O S S N.C
Positive terminal of Pump Capacitor. Positive terminal of Storage Capacitor. DMOS Half Bridge Output and Input A for Bemf sensing. Power Section Supply Terminal. 12V supply. Open Terminal
14 15 16 18 19 20 21 22 23 24 25 26 27
8 9 10 12 13 14 15 16 17 18 19 20 21
Tdly(0) Tdly(1) Tdly(2) OTWARN SELECT POLE PWM TIMER PWM/LINEAR OUTPUT ENABLE SEQUENCE SEQ INCREMENT SYSTEM CLK MONO/SEQ. INC. CONTROL Falign
I I I O I I I I I I I I I
Three bits that set the Delay between the detection of the Bemf zero crossing, and the commutation of the next Phase.
Overtemperature Warning Output Selects # of Motor Poles. A zero selects 8, while a one selects 4 poles. Capacitor connected to this pin sets the maximum time allowed for 100% duty cycle during PWM operation Selects PWM or Linear Output Current Control Tristates Power Output Stage when a logic zero. Rising edge will initiate start-up. A Braking rountine is started when this input is brought low. A low to high transition on this pin increments the Output State Sequencer. Clock Frequency for the system timer/counters. A logic one will disable the Monotonicity Detector and Sequence Increment functions. Reference Frequency for the opt. Auto-Start Algorithm. If int. start up is not used, this pin must be connected to the System Clock. Output of the PWM Comparator 5V Logic Supply Voltage. Motor Once-per-Revolution signal. Voltage at this input controls he Motor Current Input to the Current Sense Amplifier. Output C connection for the Motor Current Sense Resistor to ground. DMOS Half Bridge Output and Input C for Bemf sensing. A series RC network to ground that defines the compensation of the Transconductance Loop.
28 30 31 33 34 35 36 37
22 24 25 27 28 29 30 31
30 35 36 37 38 39, 40 42, 43 44
PWM COMP Vlogic Fmotor Vcontrol CSA INPUT Rsense 2 OUTPUT C gm COMP
O S O I I O I/O I
4/31
L6238S
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64 38 41 43 44 32 35 37 38 45 51 54 55 Name GATE DRIVER MASK/DELAY CENTER TAP PWM/SLEW I/O I/O O I I Function Drivers the Ext. PFET Gate Driver for Higher Power applications. This pin must be grounded if an external driver is not used. Internal Logic Signals used for production Testing Motor Center Tap used for differential BEMF sensing. R/C at this input set the Linear Slew Rate and PWM OFF-Time
Figure 1: Brake Delay Timeout vs Cbrake (Rbrake = 1Meg)
TBD (s)
D95IN274
Figure 2: Linear Slew Rate vs Rslew
SVR (V/s)
D95IN275
3.0
3.0
1.0
1.0
0.3
0.3
0.0
0.0
0.0
0.3
1.0
3.0
Cb(F)
10
30
100
300
Rs(K)
Figure 3: PWM Off - Time vs Rslew/Coff
Figure 4: PWM Limit Time - Out vs Ctimer
PWM (s)
D95IN276
PWM (s)
D95IN277
30
10
30
3
1
100
300
Coff(pF)
10
100
300
Ctimer(pF)
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L6238S
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C; VA = VPwr = 12V; Vlogic = 5V; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
GENERAL
Vanalog Ianalog Vlogic Ilog ic Analog Supply Voltage Analog Supply Current Logic Supply Voltage Logic Supply Current Run Mode Vlogic = 5.5V Brake Mode Run Mode VA = 13.5V Brake Mode VA = 13.5V 4.5 1 100 10.5 1.5 2.7 280 5.0 2 500 13.5 4.5 800 5.5 3.2 1000 V mA A V mA A C C C mA V V/s V/s mA 0.7 0 5.0 10 V V A s V V A mV V
THERMAL SHUTDOWN
* Tsd * Thys * Tew Shut Down Temperature Recovery Temperature Hysteresis Early Warning Temperature 150 30 Tsd-25 180
POWER STAGE
RDS(on) Io(leak) VF dVo/dt Igt VGate-Drive VCtrl-Range Iin(VCtrl) Output ON Resistance per FET Output Leakage Current Body Diode Forward Drop Output Slew Rate (Linear) Output Slew Rate (PWM) Gate Drive for Ext. Power DMOS Ext Driver Disable Voltage Voltage Control Input Range Voltage Control Input Current Vcontrol = 1V; Vsns = 0V; VA = 10.5V Tj = 25C; VA = 10.5V Tj = 125C; VA = 10.5V Vpwr = 15V Im = 2.0A Rslew = 100K 0.15 10 4.5 0.30 0.20 0.26 0.40 1 1.5 0.45 150
PWM OFF-TIME CONTROLLER (Rslew = 100K, Coff = 120pF)
Toff Vchrg Vtrip OFF Time Capacitor Charge Voltage Lower Trip Threshold VA = 10.5V 9 2.31 11 2.65 1.25 14 3.1
PWM LIMIT TIMER
Ichrg Vchrg Vtrip Capacitor Charge Current Capacitor Charge Voltage Lower Trip Threshold VPWM Timer = 0V; VA = 10.5V VA = 10.5V 10.0 3.0 20.0 3.5 100 30 4.0 400
BEMF AMPLIFIER
ZinCT VBemf Center Tap Imput Impedance Minimum Bemf (Pk-Pk) 20 60 30 40 K mV A V/V V/s
CURRENT SENSE AMPLIFIER
Isnsin Gv SR Input Bias Current Voltage Gain Slew Rate VA = 13.5V 3.8 0.33 4.0 0.8 10 4.2
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L6238S
ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
BRAKE DELAY
Vchrg Iin Iout3 VThres Capacitor Charge Voltage Input Current Source Current Delay Timer Low Trip Threshold RT = 50K Vin = 5.0V VA = 10.5V 0.5 1.2 1.8 2.8 8.8 9.6 10.5 500 V nA mA V
CHARGE PUMP
Vout Fcp Iin Ibrkdly Ibrake Storage Capacitor Output Voltage Charge Pump Frequency Vstorage Input Current (Run Mode) Vstorage Leakage Current (Brake Delay Mode) Vstorage Leakage Current (Brake Mode) Vstorage = 12V; VA = Vlogic = 0 Vstorage = 12V; VA = Vlogic = 0 Vstorage = 12V; VA = Vlogic = 0 0.4 0.1 VA = 10.5V; Iout = 500A 17 140 450 25 1 1 V KHz A A A
SEQUENCE INCREMENT
tseq Time Between Rising Edges 1 s
OUTPUT TRANSCONDUCTANCE AMPLIFIER Note: Measure at OTA Comp. pin.
Voh VoutL Isource Isink Voltage Output High Output Voltage Output Voltage Output Sink Current 40.0 40.0 VA = 10.5V 10 2.0 0.5 V V V A
LOGIC SECTION
VinH VinL VinH VinL IinH IinL VoutL VinL Fsys toff /ton Input Voltage (All Inputs Except Run/Brake Run/Brake Input Voltage Input Current -1.0 Output Voltage System Clock Frequency Clock ON/OFF Time Vsink = 2.0mA Vsource = 2.0mA 0.5 4.5 8.0 20 12.0 Vlogic = 4.5 to 5.5V Vlogic = 4.5 to 5.5V 3.5 1.5 2.0 1.0 1.0 V V V V A mA V V MHz ns
Phase Delay Truth Table
Tdelay (2) 1 1 1 1 0 0 0 0
(*) Input Default
Tdelay (1) 0 0 1 1 0 0 1 1
Tdelay (0) 1 0 1 0 1 0 1 0
Commutation Phase Delay, in Electrical Degrees 2.0 9.4 18.80 20.68 22.56 24,44 (*) 26.32 28.20
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0.1F
0.068F
8/31
VLOGIC(5V) 27K 10K 3.6K Vpower 44 OUT A 38 4 5 8 SENSE -INPUT SENSE +INPUT OUT B Rs 0.4 SENSE OUT 360K 12 14 13 DA2OUT 360K ERROR AMP OUTPUT 11 15 31 CP1 CP2 V PROG 33 10 V CC/2 GAIN1-IN DA0Out GAIN2-IN 100K 10K 360K VCM 9 37 42 V CC SENSE GATE DRV V LOGIC 26 39 22 19 20 21 22 23 24 25 26 36 28 27 18 6,7,17,29,39,40 41 VPUMP 220pF 0.068F 1F 0.01F Rprogram
D95IN278
L6238S
Figure 1-1
60-90Hz 12V Note: If the internal Start-up Algorithm is not used, connect this pin to SYS_CLK
22F MONO SEQ. VLOGIC POR 43 35 OUT ENA data(0) data(1) data(2) data(3) data(4) data(5) RUN/BRK VCTRL SEQ INC F MTR OT WARM T DLY(0) T DLY(1) WR A0 A1 PWM TMR GND POR DLY 3 14 CS T DLY(2) data(7) GATE DRIVE 38 23 33 34 31 18
0.1F
F ALIGN
VPWR
VANLG
OUT A
10
27
11,42
12
CTR TAP
43
FUNCTIONAL DESCRIPTION 1.0 INTRODUCTION 1.1 Typical Application In a typical application, the L6238S will operate in conjunction with the L6244 Voice Coil Driver as
OUT B
1
OUT C
36
RSENSE
L6238S
CONTROLLER
data(6)
L6244
VOICE COIL DRIVER
6.33 15 16
CSA
4.35 14
SPINDLE MOTOR DRIVER
CHRG PUMP 2
34
5
10nF
CHRG PUMP 1 37 BRK DLY 10K GND 3
8
25 GM COMP 100K
9
44
20 6,7,17, 29,39,40
SYS CLK
CHRG PUMP 3 4.7F
PWM SLEW
shown in Fig. 1-1. This configuration requires a minimum amount of external components. 1.2 Input Default States Figure 1-2 depicts the two possible input structures for the logic inputs. If a particular pin is not
8.12MHz
400pF
L6238S
Figure 1-2 reaches the nominal speed. 4) Park When Run/Brake is brought low, energy to park the heads may be derived from the rectified Bemf. The energy recovery time is a function of the Brake Delay Time Constant. In this state, the quiescent current of the device is minimized (sleep mode). 5) Brake After the Energy Recovery Time-Out, the device is in Brake, with all lower Drivers in full conduction. There are two mutually exclusive conditions which may be present during the Tristate Mode (wake up): a)the spindle is stopped. b)the system is still running at a speed that allows for resynchronization. In order to minimize the ramp up time, the microcontroller has the possibility to: check the SPIN SENSE pin, (which toggles at the Bemf zero crossing frequency) enable the power to the motor based on the previous information. Otherwise the P may issue a Brake command, followed by the startup procedure after the motor has stopped spinning. 2.0 STATE DIAGRAMS 2.1 State Diagram Figure 2-1 is a complete State Diagram of the controller depicting the operational flow as a function of the control pins and motor status. The flow can be separated into four distinct operations. 2.2 Align + Go Figure 2-2 represent the normal flow that will achieve a spin-up of the spindle motor using the internally generated start up algorithm. Upon power up, or from any state with Run/Brake low the controller first sets the state machine for State=1 with the Outputs Tristated. The period counter that monitors the time between zero crossing is stopped, analog with the phase and mask delay counters. When Run/Brake is brought high, the motor is in the first part of the align mode at State 2 (Output A high and Output C low). If Output Enable is high, the controller first checks to determine if the motor is still spinning for a time of 21 (with Sys_Clk = 10MHz). The drivers are now enabled and after the align time-out, (64/Falign), the sequencer double increments the outputs to State 4 (Output B high and Output A low). The first part of this align mode is used to reduce the effects of stiction
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VLOGIC
VLOGIC
10A 330 330 10A
PULL-UP
D95IN279
PULL-DOWN
used in an application, it may either be connected to ground or VLOGIC as required, It may also be simply left unconnected. If no connection is made, the pin is either pulled high or low by internal constant current generators as shown above. A listing of the logic and clock inputs is shown in Table 1 with the corresponding default state. Table 1
Pin Function Tdly (0,1,2) Select Pole PWM/Linear Output Enable Run/Brake Sequence Increment System Clock Faling Configuration Pull-Down Pull-Down Pull-Down Pull-Down Pull-Up Pull-Down Pull-Up Pull-Up
1.3 Modes of Operation There are 5 basic modes of operation. 1) Tristate When Output Enable is low, the output power drivers are tristated. 2) Start-Up With Output Enable high, bringing Run/Brake from a low to a high will energize the motor and the system will be driven by the Fully-Integrated StartUp Algorithm. A user-defined Start-Up Algorithm, under control of a MicroProcessor, can also be achieved via the sequence increment input. 3) Run Run mode is achieved when the motor speed (controlled by the external microprocessor)
L6238S
Figure 2-1
POR=0 FROM ANY STATE (FOR IS GENERATED INTERNALLY BY MONITORING VLOGIC)
RUN/BRAKE=0 FROM ANY STATE
STATE = 1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP
SEQLNC=1 & OUTENA=0 RUN/BRK=X
INT. START-UP DISABLED MIN. CLOCK DELAY LOAD MIN. DELAY LOAD MIN. MASK***
RUN/BRK=1 & OUTENA=1
DRIVERS ON PERIOD COUNT DELAY COUNT
RUN/BRAKE=1
SEQINC=0
SEQINC=1
STATE=STATE+1* MASK COUNT SEQINC=0 BEMF
MASK COUNT BEMF SEQINC=1
LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT**
SEQINC=1 DRIVERS OFF MIN CLOCK DELAY LOAD MIN MASK*** PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1 OUTENA=1 OUTENA=1 OUTENA=0 BEMF DRIVERS OFF STATE=STATE+1 MIN CLOCK DELAY LOAD MIN DELAY LOAD MAX MASK DELAY COUNT STATE=STATE+1 MASK COUNT 2 21 SYS_CLK 2 21 DRIVERS ON PERIOD STOP DELAY STOP MASK STOP 64/FALIGN RUN/BRK=0 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP STATE=STATE+2 BEMF 192/FALIGN OUTENA=0 RUN/BRK=0 221 DRIVERS OFF SYS_CLK STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT DRIVERS OFF MONO=0** SYS_CLK LOAD DELAY=MIN LOAD MASK=MIN RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT OUTENA=1 CHECK FOR Zc OUTENA=1 BEMF BEMF LOAD MIN. DELAY LOAD MIN. MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT FROM ANY STATE WITH SEQ_INC=0
STATE=STATE+1
RETURN TO PREVIOUS STATE (CHANGING SEQINC=1)
STATE=STATE+2
BEMF
* VALID IF SEQINC=0, AND DELAY TIMES OUT ** CLOCK DELAY=F(TDLY_[2:0]) WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES)
OUTENA=1
BEMF BEMF RUN MODE
DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT
OUTENA=0
DRIVERS OFF MIN CLOCK DELAY PERIOD STOP
ALIGN & GO MODE BEMF
RESYNCHRONIZATION MODE
D95IN280
* CLOCK DELAY=F(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF1: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 **MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE) ***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2s)
After the next align time-out 192/Falign), the controller enters the Go mode, were the sequencer again double increments the output phase upon detection of the motor's Bemf. The align time-out may be optimized for the application by changing the Faling reference frequency. A Watch-Dog Timer protection feature is built into the control logic to monitor the Falign pin for a clocking signal. This circuitry, shown in Figure 2-3 will prevent start up the device if the Falign clock is not present.
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Without this feature, the output would remain in the first phase under high current conditions, if the clock were not present. If the external sequencer is used to provide start up, the system clock may be tied to the Falign pin to satisfy the requirements of the Watch-Dog Timer. 2.3 Resynchronization If power is momentarily lost, the sequencer can automatically resynchronize to the monitored
L6238S
Figure 2.2 Bemf. This resychronization can either occur whenever Output Enable or Run/Brake is first brought low then high. Referring to figure 2-4, the "Hold for Resync" state is brought low. The controller leaves this state and enters "Start Resync" when Output Enable is high. Figure 2.3: Watch-Dog Timer
OVER TEMP SHUTDOWN
STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT
POR=0 FROM ANY STATE
RUN/BRK=0 FROM ANY STATE
STATE=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP
DRIVERS ON PERIOD STOP DELAY STOP MASK STOP
64/FALIGN RUN/BRAKE=1
CHECK FOR Zc 192/FALIGN
DRIVERS OFF MIN CLOCK DELAY LOAD MIN DELAY LOAD MIN MASK PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1
BEMF
BEMF
S
CHECK FOR Zc DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT 2 21 SYS_CLK
Q
TO START-UP LOGIC
BEMF
S
D95IN310
Q
BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 ***MIN MASK=192/SYS_CLK (I.E. WITH SYS_CLK=10MHz, MIN MASK=19.2s)
OUTPUT ENABLE
RUN/ BRAKE
FALIGN
D95IN311
Figure 2-4
LOAD MIN DELAY LOAD MIN MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT
BEMF
OUTENA=1
BEMF
CHECK FOR Zc
BEMF
RUN/BRK=0
LOAD DELAY=MIN LOAD MASK=MIN PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT
BEMF
OUTENA=1
DRIVERS OFF
MONO=0**
BEMF
BEMF
RUN MODE
DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAYH COUNT* STATE=STATE+1 MASK COUNT
OUTENA=0
DRIVERS OFF MIN CLOCK DELAY PERIOD STOP
HOLD FOR RESYNC RESYNCHRONIZATION MODE
D95IN312
*CLOCK DELAY=(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 ** MONO=0 WHEN FREQ (BEMF)=2*FREQ(PHASE) *** MIN MASK=192/SYS_CLK(I.E.WITH SYS_CLK=10MHz, MIN MASK=19.2s)
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L6238S
Figure 2-5
POR=0 FROM ANY STATE
STATE=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP SEQINC=1 & OUTENA=0 RUN/BRK=X
INT START-UP DISABLED MIN CLOCK DELAY LOAD MIN DELAY LOAD MIN MASK
RUN/BRK=1 & OUTENA=1
DRIVERS ON PERIOD COUNT DELAY COUNT SEQINC=0 SEQINC=1
STATE=STATE+1 MASK COUNT BEMF SEQINC=0 LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT** BEMF
MASK COUNT
SEQINC=1
SEQINC=1 FROM ANY STATE WITH SEQ_INC=0
STATE=STATE+1
RETURN TO PREVIOUS STATE (CHANGING SEQINC=1)
D95IN313
*VALID IF SEQINC=0, AND DELAY TIMES OUT **CLOCK DELAY=F(TDLY_[2:0]) WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES)
If zero crossings are detected, the sequencer will automatically lock on to the proper phase. This resynchronization will take effect with the motor speed running as low as typically 30% of it's nominal value. 2.5 External Sequencing Although the user-defined Start-Up Algorithm is flexible and will consistently spin up a motor with no external interaction, the possibility exists where certain applications might require complete microprocessor control of start-up. The L6238S offers this capability via the SEQUENCE INCREMENT input. Referring to figure 2-5, during initial power-up with Output Enable low, the controller is in the "Hold and Wait for Decision" state. If the SEQUENCE INCREMENT pin is brought high during this state, the Auto StartUp Algorithm is disabled and the sequencer can be controlled externally. When Output Enable and Run/Brake are brought high, the sequencer is incremented on each positive transition o the SEQUENCER IN12/31
CREMENT pin. During the time that this pin is high, all Bemf information is masked out. When it is low, the Bemf information can be detected normally after the internal mask time. The minimum mask time is 192/Sys_Clk (i.e. with Sys_Clk = 10MHz, min. mask = 19.2s) Therefore to insure that the sequencer is under complete control of the state machine, the time that the SEQUENCE INCREMENT pin is held low should be much less then the min. mask time, but greater then 1s. When the motor has reached a predetermined speed, the SEQUENCE INCREMENT pin can be left low and the L6238S Motor Control logic will take over and automatically spin up the motor to the desired speed . 3.0 START-UP ALGORITHMS 3.1 Spin-Up Operation The spin operation can be separated into 3 parts: 1) Open Loop Start-Up - The object is to create motion in the desired direction so that the Bemf voltages at the 3 motor terminals can provide reliable information enabling a transition to closed loop operation.
L6238S
Figure 3-1: Align+Go
RUN/BRAKE
ALIGNMENT GO
SEQUENCER
DOUBLE INCREMENTS *0.711s *2.133s
AOUT 1
10V
BOUT 2
10V
COUT 3
10V
STATE 2 A=HIGH B=FLOAT C=LOW
STATE 4 A=LOW B=HIGH C=FLOAT
STATE 6 A=FLOAT B=LOW C=HIGH
* FALIGN=90Hz
500ms/DIV
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2) Closed Loop Start-Up - The Bemf voltage zerocrossings provide timing information so that the motor can be accelerated to steady state speed. 3) Steady-State Operation - The Bemf voltage zero-crossings provide timing information for precision speed control. The L6238S contains features that offer flexible control over the start-up procedure. Either the onboard Auto-Start Algorithm can be used to control the start-up sequence or more sophisticated extenal start-up algorithms can be developed using the Serial Port and key control/sense functions brought out to pins. 3.2 Auto-Start Algorithm When initially powered up, the controller defaults to the internal AutoStart Mode. When Run/Brake is low, the L6238S is in brake mode, and the Auto-Start Algorithm is reset. In the brake mode, all of the lower DMOS drivers are ON, and the up-
per drivers are OFF. The Auto-Start Algorithm is based on an Align & Go approach and can be visualized by referring to Figure 3-1. Shown are the Run/Brake control signals, sequencer function, and the three output voltage waveforms. Referring to figure 3-1, the following is the sequence of events during Auto-Start: With Output Enable = 1, Run/Brake = 0 - State Machine is set to State 1 with the drivers Trisatted. Alignment Phase (1) Run/Brake = 1 - Output Stage is sequenced to State 2 and the drivers energized with OUTPUT A high and OUTPUT C low for 64/Falign seconds. Alignment Phase (2) - Output Stage is double sequenced to State 4 with OUTPUT B high and OUTPUT A low for
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L6238S
192/Falign seconds. - During the alignment phase, the SEQ INCREMENT signal is ignored. Go Phase - The internal sequencer double increments the output stage to State 6, which should produce torque in the desired direction. - with SEQ INCREMENT held low, the sequencer is now controlled by the Bemf zero crossings, and the motor should ramp up to speed. 3.3 Externally Controlled Start-Up Algorithms Enhanced Start-Up Algorithms can be achieved by using a Processor to interact with the L6238S.' The L6238S has the ability to transition to Closed Loop Start-Up at very low speeds, reducing the uProcessor task to monitoring status rather than real time interaction. Thus, it is a perfect application for an existing Processor. The following control and status signals allow for very flexible algorithm development: SEQ_INCR A low to high transition at this input is used to increment the state of the power output stage. It is useful during start-up, because the Processor can cycle to any desired state, or cycle through the states at any desired rate. When held high, it inhibits the BEMF zero crossings from incrementing the internal sequencer. SPIN SENSE This output is low until the first detected Bemf zero crossing occurs. It then toggles at each successive zero crossing. This signal serves as a motion detector and gives useful timing information as well as the slope of the Bemf. 3.4 Start Up Approaches Align & Go Approach The Align & Go approach provides a very time efficient algorithm by energizing the coils to align the rotor and stator to a known phase. This approach can be achieved via the sequencing SEQ INCR. SPIN SENSE can be monitored to assure that motion occurred. Once ample time is given for alignment to occur, SEQ INCR can be double incremented, and the SPIN SENSE pin can be monitored to detect motion. When SEQ INCR is pulled low, control is transferred to the internal sequencer, and the L6238S finishes the spinup operation. If no motion is detected, SEQ INCR can be incremented to a different phase and the process can be repeated. The alignment phase may cause backward rotation, which on the average will be greater than the Stepper Motor approach.
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The Auto-Start algorithm described earlier is an Align & Go approach. The main advantages of the integrated Auto-Start are that the P is not involved real-time, and there are a minimum of interface pins required to the spindle control system. Stepper Motor Approach This approach minimizes backward rotation by sequencing SEQ INCR at an initial rate that the rotor can follow. Thus, it is driven in a similar fashion to a stepper motor. The rate is continually increased until the Bemf voltage is large enough to reliably use the zero-crossings for commutation timing. SEQ INCR is held low, causing control to be passed to the L6238S's internal sequencer as in the Align & Go approach. The Stepper Motor approach takes longer than the Align & Go approach because the initial commutation frequency and subsequent ramp rate must be low enough so that the motor can follow without slipping. This implies that to have a reliable algorithm, the initial frequency and ramp rate must be chosen for the worst case motor under worst case conditions. 4.0 MOTOR DRIVER 4.1 Output Stage The output stage forms a 3-Phasefull wave bridge consisting of six Power DMOS FET High output currents are allowed for bbrief periods. High output currents are allowed for brief periods. Output Power exceeding the stand-alone power dissipation capabilities of the L6238S can be increased with the addition of an external P-FET or by the use of Pulse-Width-Modulation. Table 4-1 is a reference diagram that lists the parameters associated with 8-pole motors operating at 3600 and 5400 RPM. Figure 4-1 represents the waveforms associated with the output stage. The upper portion of figure 4-1 shows the flow of current in the motor windings for each of the 24 phase increments. A rotational degree index is shown as a reference along with a base line to indicate the occurrence of a zero crosing. The output waveforms are a digitally reproduced voltage signals as measured on samples.The feedback Input is multiplexed between the internal Bemf Zero Crossing Detector and an externally provided sync pulse (EXT INDEX) Shown in figure 10 is the classical state diagram for a phase detector along with waveform examples. A typical sequence starts when the outputs switch states. Referring to figure 4-1, during phase 1, output A goes high, while outputB is low. During this phase, output C is floating, and the Bemf is monitored. The outputs remain in this state for 60 electrical degrees as indicated by the first set of dashed lines. After this period the out-
L6238S
Table 4-1
Rotational Speed Rotational Frequency Rotational Period Electrical Period Phase Period
3600rpm 60Hz 16.667ms 4.167ms 694.5s
5400rpm 90Hz 11.111ms 2.778ms 463.0
Figure 4-1: Waveforms
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L6238S
put switched to phase 2 with output A high and C low with the Bemf amplifier monitoring output B. In order to prevent commutation current noise being detectedm as a false zero crossing, a masking circuit automatically blanks out all incoming signals as soon as a zero crossing is detected. When the next commutation occurs an internal counter starts counting down to set the time that the masking pulse remains. The counter is initially loaded with a number that is equal to time that is always 25% of the previous phase period or 15 electrical degrees. The timeout of the masking pulse shown for reference at the bottom of figure 4-1. Thus the actual masking period is the total of the time from the detected zero crossing to the phase commutation, plus 25% of the previous period. The mask pulse operation is further discussed in section 4.6, Slew Rate Control and PWM operation. After the masking period, the Bemf voltage at output B is monitored for a zero crossing. Upon detection of the crossing, the output is commutated after the selected phase delay insuring maximum Figure 4-2 torque. The spin sense waveform at the bottom of the figure indicates that this output signal toggles with each zero crossing. 4.2 Brake Delay When Run/Brake is brought low, a brake is initiated. Referring to figure 4-2, SW1 is opened and the brake delay capacitor, Cbrake, is allowed to discharge towards groun via Rbrake. At the same time, switches SW2 through SW7 bring the gates of the output FETs to ground halting conduction, causing the motor to coast. While the motor is coasting, the Bemf is used to park the heads. When Cbrake reaches a voltage that is below the turn ON threshold of Q1, Switches SW8, 9, and 10 bring the gates of the lower drivers to Vbrake potential. This enables the lower FETs causing a braking action. The analog and logic supplies are not monitored in the L6238S, since the L6244 already monitors this voltage and initiates a Park function when either supply drops to a predeterminated level.
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L6238S
Figure 4-3
4.3 Charge Pump The charge pump circuitry is used as a means of doubling the analog supply voltage in order to allow the upper N-channel DMOS transistors to be driven like P-channel devices. The energy stored in the reservoir capacitor is also used to drive the lower drivers in a brake mode if the analog supply is lost. Figure 4-3 is a simplified schematioc of the charge pump circuitry. Figure 4-4
A capacitor, Cpump, is used to retrieve energy from the analog supply and then "pumps" it into the storage capacitor, Cresvr. An internal 300KHz oscillator first turns ON Q2 to quickly charge Cpump to approximately the rail voltage. The oscillator then turns ON Q1 while turning OFF Q2. Since the bottom plate of Cpump, is now effectively at the rail voltage via D2. A zener-referenced series-pass regulator supplies
VPOWER VPUMP SW2 UPPER A VCTRL + L1 1 0 I1 Islew 1 0 I2 Islew CSA VANALOG Q3 Q4 Cfet Cfet Q1
OUTPUT BC
L2
A2 SW3
L3
OUTA Q2 RSENSE
LOWER A
A3 X4
RS Q5 PWM SLEW/RC RSLW
SLEW RATE REFERENCE CURRENT
3.1V
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L6238S
a voltage, Vbrake, during brake mode. The maximum capacitance specified for the Storage Capacitor is 4.7F.For applications requiring a larger value, an external diode should be connected between Vanalog and the Storage Capacitor to prevent excessive inrush current from damaging the charge pump circuitry. A small value resistor (i.e. 50W) may instead be inserted in series with the Storage Capacitor to limit the inrush current. 4.4 Linear Motor Current Control The output current is controlled in a linear fashion via a transconductance loop. Referring to Figure 4-4 the sourcing FET of one phase is forced into full conduction by connecting the gate to Vpump, while the sinking transistor of an appropriate phase operates as a transconductance element. To understand the current control loop, it will be assumed that Q2 in figure 4-4 is enabled via SW3 by the sequencer. During a run condition, the current in Q2 is monitored by a resistor Rs connected to the Rsense input. The resulting voltage that appears across Rs is amplified by a factor of four by A3 and is sent to A2 where it is compared to the Current Command Signal. A2 provides sufficient drive to Q2 in order to maintain the motor speed at the proper level as commanded by the Speed Controller. 4.5 Transconductance Loop Stability The RC network connected to the Compensation pin provides for a single pole/zero compensation scheme. The pole/zero compensation scheme. Figure 4-5 The pole/zero locations are adjusted such that a few dB of gain (typ. 20dB) remains in the transconductance loop at frequencies higher than the zero. The inductive characteristic of the load provides the pole necessary for loop stability. Thus the loop bandwidth is actually limited by the motor itself. Figure 4-5 shows the complete transconductance loop including compensation, plus the response. The Bode plot depicts the normal way to achieve stability in the loop. The pole andzero are used to set a gain of 20dB at a higher frequency and the pole of the motor cuts the gain to achieve stability. Loop instability may be caused by two factors: 1)The motor pole is too close to the zero. Referring to figure 4.6, the zero is not able to decrement the shift of phase, and when the effect of the pole is present, the phase shift may reach 180 and the loop will oscillate. To rectify this situation, the pole/zero must be shifted at lower frequencies by increasing the compensation capacitor. Figure 4-6
Figure 4-7
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L6238S
Figure 4-8 turbance when one motor phase turns OFF and another turns ON because the FET turn-OFF time is much shorter than the L/R rise time. Abrupt FET turn-OFF without a proper snubbing circuit can even cause current recirculation back into the supply. However, the need for a snubber circuit can be eliminated by controlling the turn-OFF time of the FETs. The rate at which the upper and lower drivers turn OFF is programmable via an external resistor, Sslew connected to the SLEW RATE pin. This resistor defines an internal current source that is utilized to limit the voltage slew rate at the outputs during transition, thus minimizing the load change that the power supply sees. To insure proper operation the range of resistor values indicated should not be exceeded and in some applications values near the end points should be avoided as discussed below. Low Values of Rslew - If a relatively low value of Rslew is selected, the resultant fast slew rate will result in increased commutation cross-over current, higher EMI, and large amount of commutation current. This last case can cause voltage spikes at the output that can go as much as lV below ground level. This situation must be avoided in this integrated circuit (as in most) since it causes unpredictable operation. High Values of Rslew - Higher values of Rslew result of course in slow slew rates at the outputs which is, under most conditions, the desired case since the problems associated with fast rates are reduced. The additional advantage is lower acoustical noise. Problems can occur though if the slew rate for a
2)The motor capacitance, CM, itself can interfere with the loop, creating double poles. If the gain at higher frequencies is sufficiently high, the double pole slope of 40dB/decade can cause the phase shift to reach 180, re sulting in oscillation. Figure 4-8 is a Bode plot showing how to correct this situation. The bold line indicates the response with relatively high gain at the higher frequencies. By leaving the pole unchanged and increasing the zero, the response indicated by the dashed lines can be achieved. 4.6 Slew Rate Control A 3-phase motor appears as an inductive load to the power supply. The power supply sees a disFigure 4-9: Effect of Slow Slew Rate.
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L6238S
Figure 4-10: External P-Fet.
given application is too slow. Figure 4-9 is an oscillograph taken on a device that had a fairly large value for Rslew and failed to spin up and phase lock a motor. The problem manifests itself as the motor begins to spin up. At lower RPMs, the Bemf of the motor is relatively small resulting in higher amounts of commutation current. In figure 4-9, the upper waveform is the voltage appearing at OUTPUT relative to the CENTER TAP input. The lower waveform is the actual output of the Bemf amplifier available on special engineering prototypes. The oscillograph was taken just as the problem occured. The period between zero crossings was ~800s resulting in a mask time period of 200s. As can be seen, the excessively long slew rate actually exceeded the mask period and was detected as a zero crossing. This resulted in improper sequencing of the outputs relative to the proper phases and caused the motor to spin down. 4.7 Ext PFET Driver The power handling capabilities of the 3 phase output stage can be extended with the addition of a single P-Channel FET.
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Figure 4-10 shows the Ext FET connection and demonstrates how the L6238S automatically senses the FETs presence. When the voltage at the Gate Drive pin is 0.7V, the output of comparator A3 goes high, removing the variable drive A1 from the internal FETs and connects them instead to Vanalog via the commutation switches to facilitate full conduction. The upper FETs drive paths are not shown for clarity. A3 also closes SW2 allowing A1 to linearly drive the external P-Channel FET Q1 via inverter A2. 4.8 Bemf Ampolifier Since no Hall Effect Sensors are required, the commutation information is derived from the Bemf voltage zero-crossings of the undriven phase with respect to the center tap. The Bemf comparator and associated signal levels are depicted in figure 4-11. For reliable operation, the Bemf signal amplitude should be a minimum of 60 mV to be properly detected. In order to provide for noise immunity, internal hysteresis is incorporated in the detection circuitry to prevent false zero crossing detection. For laboratory evaluation purposes, a simple re-
L6238S
Figure 4-11: Bemf Amplifier.
VoBEMF
ViBEMF(mV) -35 -25 0 25 35
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SLOPE=0
SLOPE=1
sistive network as shown in figure 4.12 can be used to emulate the Bemf of the motor. The actual Bemf zero-crossing is 30 electrical degrees (50% of a commutation interval) away from the optimal switch point. A digital counter circuit measures 50% of the previous interval to determine the next interval's commutation delay from the zero crossing. During the low RPM stages of start up the long commutation intervals may cause the counter to overflow, in which case 50% of the max count will be less than 50% of the ideal commutation interval. Therefore, the torque Figure 4-12: Bemf Emulator
will not be optimal until the desired commutation interval is less than the dynamic range of the counter. 4.9 Center Tap Protection Spindle Motors with a high number of windings exhibit a transformer coupling effect that in some cases can cause relatively high currents to flow through the center tap input. Current flowing out of the center tap pin as high as 25mA has been observed with certain motors. Figure 4-13
R1 1K
TO CENTER TAP INPUT
DS1
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L6238S
The high current flows from the grounded substrate of the integrated circuit (p-type material), through one or more epitaxial pockets (n-type material) and out the center par pin. This current can cause adverse operation of the controllet due to substrate injection and might possibility damage the internal metalization runs. The normal current for this input is in the 200A range. Referring to figure 4-13, a simple protection scheme consisting of a 1K resistor and a low current Schottky diode should be added if the application causes excessive current (i.e. >1mA) to flow through the center tap pin. 5.0 PWM MOTOR CURRENT CONTROL A unique feature of the L6238S in the optional Pulse Width Modulation (PWM) control of motor current. Using Variable-frequency, Constant-OFF time Current-Mode control, the L6238S can drive higher power motors without the need for external drivers, while minimizing internal power dissipation. Additional benefits include reduced power supply consumption (up to 50% savings) and lower wattage requirements for the current sensing resistor. Constant-OFF time Current-Mode control, operates on the principle of monitoring the motor current and comparison it to a reference or control level. Figure 5-1
VPOWER VPUMP VANALOG Q1 Q2 UPPER A N3 SW2 L1 Q4 Cfet I1 Islew L2 OUTPUT BC
When the motor current reaches this commanded level, the output drivers turn OFF and remain OFF for a Constant-OFF time. After this OFF time the drivers turn back ON to repeat the cycle. Figure 5.1 is a block diagram of the PWM control circuitry. When using PWM as opposed to linear control, two changes are made to the control loop: 1.The slew rate control is disabled, allowing the outputs to slew at a minimum rate of 10V/s. This is accomplished by closing SW3 and SW5. 2.The OTA amplifier is taken out of the control loop via SW6. The lower drivers are now driven into hard conduction by tying the gates to the analog supply during the On time of the PWM cycle. The current in the motor windings is monitored via the voltage dropped in the sensing resistor, Rsense . This voltage is multiplied by a factor of 4 in the Current Sense Amplifier (CSA) and sent to negative input of the PWM Comparator (A2). The control voltage, Vcontrol, is applied to the positive input of A2. When the output of the CSA reaches a level that is equal to the commanded level, the output of A2 switches low, toggling the latch comprised of N1 and N2. This causes the upper drivers to turn off and opens SW1. Q3 turns OFF allowing the Constant-OFF time capacitors,
1 0
PWM/LIN CONTROL SLEW RATE REFERENCE Q3 CURRENT
SW3 L3
SW1 OUTA LOWER A 3.1V SW5 SW4 1 0 Cfet I2 Islew SW6 A1 N1 Q5
RSENSE
VANALOG 1 0
A3 PWM/SLEW 1.2V + -
FROM TRANS. LOOP N2 + A2 VCTRL X4 CSA
RSLEW
COFF
CSA
RSLW
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L6238S
Coff to discharge to dischargte through Rslew, initiating the Constant-OFF time-out. When the voltage on Coff reaches 1.2V, comparator A1switches state toggling the latch in the opposite state, turning the upper driver back ON. SW1 also closed quickly charging up Coff for the next cycle. 5.1 PWM Design Considerations In order to select the parameters associated with PWM operation, the following factors must be taken into consideration: 1. PWM Switching Frequency 2. Duty Cycle 3. Motor Currents 4. Minimum ON Time 5. Noise Blanking 6. Bemf Masking/Sampling 5.1.1. PWM Switching Frequency The PWM switching frequency Fpwm is found from: Fpwm = 1 Ton + Toff (5.1.1)
Q1 D1 L1 OUTPUTA Q2 D2 D4 L2 OUTPUTB Q4 D3 Q3
Figure 5-2
VPOWER
Q1 D1 L1 OUTPUTA Q2 D2 D4 L2 OUTPUTB D3
Q3
Q4
RSENSE RSNS
D95IN319
Figure 5-3
VPOWER
where: Ton = The time required for the motor current to reach the commanded level. Toff = The programmed OFF time. The two main considerations for this parameter are the minimum and maximum switching frequency. The maximum switching frequency occurs during the Start-up and should be kept below 50KHz due tointentional bandwidth limitations and output switching losses. 5.1.2 Duty Cycle Besides reducing the power dissipation of the controller output stage, running in PWM offers 2 additional "free" benefits: A. Reduced Powe Supply Current at Start Up B. Lower Power Rating for the Motor Current Sense Resistor. Figure 5-2 is the current path during the ON time of a phase period. The current from the supply passes through the upper sourcing DMOS, Q3 transistor through the two driven winding, the lower DMOS, Q2 and finally through the current sensing resistor Rsns. Since both Q3 and Q4 are ON, while Q3 is turned OFF. The voltage, causing the current to continue to flow through Q2, and Q4. If the duty cycle is nearor at 50%, then for 1/2 the PWM cycle, no current is flowing from the power supply or the sense resistor while current is still flowing in the motor. This lowers the requirement
RSENSE RSNS
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for both the Power Supply and the Power Rating for the sensing resistor. 5.1.3 Motor Currents
Note: It is not the objective of this section to describe the principles of brushless DC motor, but to provide sufficient information about the parameters associated with PWM operation in order to optimize an application.
A simplified model of a motor is shown in figure 54. For this discussion, lower order effects due to mutual inductance between windings, resistance due to losses in the magnetic circuit, etc. are not shown. The motor at stall is equal to a resistance, Rmtr, in series with an inductance, Lmtr. When the motor is rotating, there is an induced emf that appears across the armaure terminals and is shown in figure 5-4 as an internally generated voltage Ibemf), Eg.
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L6238S
Figure 5-4 The additional resistance associated with the output stage and sensing resistor are also in series with the motor. If we let Rs equal the total series resistence:
Lmtr
Rs = 2*RdsON + Rmtr + Rsense
Rmtr + Eg D95IN321
(5.1.5)
then (5.1.4) becomes: V = Lmtr dimtr
dt
Rs imtr + Eg
(5.1.6)
The relation between these variables is given by: V = Lmtr where: V imtr Lmtr Rmtr Eg = = = = = Applied Voltage Motor Current Total inductance windings of the motor
Rmtr KEW
dimtr
dt
Rmtr imtr + Eg
(5.1.2)
Figure 5-6
Lmtr
Resistance in series with the motor The internally generated voltage of the motor, proportional to the motor velocity
+ LOWER Rdson LOWER Rdson
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Since: = KE (5.1.3) Eg The above equations can be combined to form the basic electrical equation for a motor: V = Lmtr dimtr
dt
Rmtr imtr + KE
(5.1.4)
Figure 5.5 is a simplified electrical equivalent of the output stage of the L6238S along with the model of the motor during the time that the Output Drives are conducting. Figure 5-5
UPPER Rdson
Figure 5-6 is an equivalent circuit of the output stage during the Constant-OFF period. During the OFF time the lower driver for the particular phase beign driven remains ON. The internally generated voltage forces the path of current though the motor, its series resistance, the RdsON of the Lower Driver and finally through the opposite lower driver. PWM Example (Refer to Figure 5-7) The following is an example on how to select the timing parameters. Given: DCStart Current Ripple Current = = = = = 1.25A 100mA 50% 880H 4.8
Lmtr
Duty Cycle Motor Interface (L) Total Series Resistance (Rs)
Rmtr +
KEW
LOWER Rdson Rsense
If the worst case start current is 1.25A and the duty cycle is 50%, then the Peak Current, It will be: 0.1 it = 1.25 +
2
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it = 1.30A
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L6238S
The Valley current, Ib will thereforebe: ib = 1.30 - 0.1A ib = 1.20A toff = During the Align and Go Phase (where the power dissipation requirements are highest, Eg is zero. The initial time required to reach the Peak current is: tinit = L I,R ln 1 V R 880e 6 1.3 4.8 ln 1 12 4.8 (5.1.7) the voltage drop remains constant across the windings. The time required for the inductor current to reach the valley current is given by: L
R
ln
It
Ib
(5.1.9)
Substituting values: toff = 880e6 1.3 ln 4.8 1.2
toff = 14.67s
Note: that the parameters for this example were selected to arrive at a 50% duty cycle. This will not always be the case due to factors such as fixed motor parameters, etc.
Substituting values: tinit =
The Constant Off timer period can be determined from: Vchrg toff = Rslew Coff ln Vtrip Where: (5.1.8) Toff = Constant-OFF Time Slew Rate Resistor Off Time Capacitor Initial Capacitor Charge Voltage Capacitor Lower Trip Threshold Rslew = Coff = (5.1.10)
tinit = 134.6s The ON time can be calculated from: V ib Rs ton = ln Rs V it Rs L Substituting values: 12 1.2 880E 6 4.8 ln ton = 4.8 12 1.3 4.8 ton = 14.67s Figure 5-7
D95IN324
Vchrg = Vtrip =
Substituting nominal values given: T off = 0.75 Rslew Coff Solving for Coff Coff = Toff 0.75Rslew
It=1.3A
Ib=1.2A Iavg=1.25A
In the example, to set the OFF timer for a 50% duty cycle: Given: Toff = 14.67s 100K (typical Value) Rslew =
Iout A 200mA 4 20s/DIV
Coff =
14.67e6 100e3
Coff 146pF 5.1.4 Minimum ON Time The bandwidth of the PWM loop was optimized to reject unwanted switching noise while providing
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During the OFF time, the motor current continues to flow through the DMOS transistors and threfore
L6238S
sufficient response, commensurate with the switching speed of the output drivers. At higher frequencies the switching losses inherent in the drivers start to negative any of the power dissipation savings gained with PWM operation. The current sense amplifier has a minimum slew rate of 0.31V/s. With a worst case Motor peak start-up current of 2.5A and Sense Resistor of 0.33, the resultant Rsense voltage would be equal to 825mV. With a minimum gain of 3.8V/V, the CSA output voltage would have to slew to 3.14V. Therefore it would require approximately 10s for the output voltage to reach the required commanded level. If an ON time were selected that was less than this time, the motor current would overshoot the desired level resulting in incorrect current control possibly exceeding the output capabilities of the drivers. 5.1.5 Noise Blanking Referring to Figure 5-8, when operating with lower levels of current (i.e. < 700mA, with Rsense = 0.33), the possibility exiss where the noise due to output Turn-ON can exceed the Commanded Current Level causing prematire TurnOFF. In order to provide noise immunity from this switching noise, a blanking circuit automatically rejects any signal appearing at the output of the CSA for a 3s period. Figure 5-9 Figure 5-9 is an additional block diagram of the PWM control loop including the noise blanking circuit. The output of A3 goes high when ever the voltage at the CSA input is more positive then the Control Voltage. This is the case when either the motor current or the turn-ON transient has reached the commanded level. The output of A3 is gates by N11. In order to provide a blanking period, Q1 is turned Figure 5-8
D95IN325
3s BLANKING PULSE
COMMANDED CURRENT LEVEL
Vrsense
1 10s/DIV
2.4V SW1 N12 N1 Q3
C1 8pF
Q1
N6
N9
+ A2 -
PWM_SLEW 1.2V R1
C3
I1 5A
N7
X4 N8 N10 N11 + A3 -
CSA INPUT
DELAY
VCONTROL
N3 CLK_BEMF N2 N4
TO OUPUT DRIVERS N5
I2 20A
PWM COMP
PWM TIMER
Q2 PWM/LIN RUN/BRAKE
C4
N12
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L6238S
ON during the Constant-OFF time, charging C1 to the internal rail. At the end of the OFF time, Q1 is turned OFF allowing current source I1 to discharge the capacitor towards ground. While the voltage on C1 is above the low input threshold of N1, the output of N1 is low, preventing any change of state at the output of N11 due to a high A3 output. When the capacitor reaches the low input threshold of N1, N1 chnges state allowing A3 to control the state of N11. 5.1.6 Masking/Bemf Sampling in PWM The method of sampling the floating phase for the bemf zero crossing defers between Linear and PWM operation. In Linear Mode, the bemf is sampled continuously after the mask time-out, until the zero crossing is detected. Then the mask is enabled for a time based on the commutation phase delay plus the additional time based on the previous period as explained earlier. With PWM operation however, the switching noise at turn ON (after the Constant-OFF time) can be significant, especially at low RPMs where the bemf is the lowest. In order to provide the greatest noise immunity in PWM, the floating phase is monitored only at the point where the output is about to be turned OFF. In operation, when the motor current reaches the commanded level, the floating phase is first monitored to determine if the bemf has crossed the zero. The output is then turned OFF for the Constant-OFF time out. As the motor current increases through, the increasing bemf causes the motor current to naturally decrease. Eventually a point is reached where the PWM is running at 100% duty cycle and the motor current cannot reach the commanded level. At this time the bemf is no longer Figure 5-10 smpled, preventing further commutation of the output. The PWM Limit Timer is used to set up a maximum ON time. When this limit is exceeded the method of sensing the bemf is essentially the same as in the case of operating in linear mode. Figure 5-10 is an oscillograph of the controller operating in PWM mode. The top trace is Aout. The 2nd trace is the voltage seen at the PWM/SLEW pin indicating the exponential discharging of the timing capacitor during the OFF time. Trace 3 is the voltage appearing on the PWM Timer capacitor, while trace 4 is the motor current. Referring again to Figure 5-9, and 5-10 transistor Q2 is turned ON at the beginning of the OFF time, discharging the external capacitor C4 to near ground level. At the end of the OFF-Time, Q2 is turned off and C4 starts charging linearly via I2. C4 is again discharged at the beginning of the OFF time and the cycle repeats. As long as C4 does not reach the threshold of A1 (typically 3.5V), the bemf is only sampled just before turnoff of the output. As the motor is starting up in figure 5-10, the duty cycle is roughly 50%. The PWM limit timer is reset to ground by the start of the OFF timer before reaching the 3.5V threshold. In figure 5-11, as the motor spins up, the on time of the output increases and the PWM limit timer reaches the 3.5V. Eventually the duty cycle reaches 100% and the sampling of the bemf is essentially the same as in the linear mode. The selection of components for the PWM timer is not critical. Since the objective is to sample the bemf only at turn OFF to maximize the signal to noise ratio, the PWM timer slope can be set up to convert to the full bemf sampling after a few revolutions of the motor when the bemf has reached an appropriatevoltage output. Figure 5-11
D95IN327
D95IN328
Aout 1
10v
Aout 1
10V
PWM/Slew 2 3
2V
PWM/Slew 2 3
2V
PWM Limit Timer 500mV
PWM Limit Timer 500mV
Iout A 4
1A
Iout A Fpwm=50KHz Coff=120pF Ctmr=220pF 20s/DIV 4
1A
Fpwm=12KHz Coff=120pF Ctmr=220pF 50s/DIV
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L6238S
PLCC44 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D d1 d2 E e e3 F F1 G M M1 1.16 1.14 14.99 1.27 12.7 0.46 0.71 0.101 0.046 0.045 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.018 0.028 0.004 mm TYP. MAX. 17.65 16.65 3.7 4.57 2.74 MIN. 0.685 0.650 0.144 0.165 0.102 0.027 0.630 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108
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L6238S
PQFP44 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 16.95 13.90 0.25 2.55 0.35 0.13 16.95 13.90 17.20 14.00 10.00 1.00 17.20 14.00 10.00 0.80 1.60 0(min.), 7(max.)
D D1 D3 A1
33 34 23 22
0.10mm .004 Seating Plane
mm TYP. MAX. 3.40 0.010 2.80 3.05 0.50 0.23 17.45 14.10 0.100 0.0138 0.005 0.667 0.547 MIN.
inch TYP. MAX. 0.134
0.110
0.120 0.0197 0.009
0.677 0.551 0.394 0.039
0.687 0.555
17.45 14.10
0.667 0.547
0.677 0.551 0.394
0.687 0.555
0.95
0.026
0.0315 0.063
0.0374
A A2
E3
E1
B
44 1 11
12
E
B C L K
e L1
PQFP44
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L6238S
TQFP64 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 0.0157 mm TYP. MAX. 1.60 0.15 1.45 0.28 0.20 0.002 0.053 0.007 0.0047 0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393 0.0295 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.0079
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TF6 Q4 P
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B
L6238S
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
(c) 1995 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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